Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. While reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon germanium, or gallium arsenide.
Semiconductor wafers (e.g., silicon wafers) may be utilized in the preparation of composite layer structures. A composite layer structure (e.g., a semiconductor-on-insulator, and more specifically, a silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the device layer is between about 0.01 micrometer and about 20 micrometers thick, such as between about 0.05 micrometer and 20 micrometers thick. In general, composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by placing two wafers in intimate contact, followed by a thermal treatment to strengthen the bond.
After thermal anneal, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques, e.g., etching or grinding, may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the carrier wafer and then slowly etched away until only a thin layer of silicon on the carrier wafer remains. See, e.g., U.S. Pat. No. 5,189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time-consuming and costly, wastes one of the substrates and generally does not have suitable thickness uniformity for layers thinner than a few microns.
Another common method of achieving layer transfer utilizes a hydrogen implant followed by thermally induced layer splitting. Particles (e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth beneath the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds deposited on the wafer during the implantation process.
The front surface of the donor wafer is then bonded to a carrier wafer to form a bonded wafer through a hydrophilic bonding process. Prior to bonding, the donor wafer and/or carrier wafer are activated by exposing the surfaces of the wafers to plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process often referred to as surface activation, which activation process renders the surfaces of one or both of the donor water and carrier wafer hydrophilic. The wafers are then pressed together and a bond is formed there between. This bond is relatively weak, and must be strengthened before further processing can occur.
In some processes, the hydrophilic bond between the donor wafer and carrier wafer (i.e., a bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as between approximately 300° C. and 500° C. In some processes, wafer bonding may occur at high temperatures, such as between approximately 800° C. and 1100° C. The elevated temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the carrier wafer, thus solidifying the bond between the donor wafer and the carrier wafer. Concurrently with the heating or annealing of the bonded wafer, the particles earlier implanted in the donor wafer weaken the cleave plane.
A portion of the donor wafer is then separated (i.e., cleaved) along the cleave plane from the bonded wafer to form the SOI wafer. Cleaving may be carried out by placing the bonded wafer in a fixture in which mechanical force is applied perpendicular to the opposing sides of the bonded wafer in order to pull a portion of the donor wafer apart from the bonded wafer. According to some methods, suction cups are utilized to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane in order to initiate propagation of a crack along the cleave plane. The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thus forming an SOI wafer.
According to other methods, the bonded pair may instead be subjected to an elevated temperature over a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to the elevated temperature causes initiation and propagation of a crack along the cleave plane, thus separating a portion of the donor wafer. This method allows for better uniformity of the transferred layer and allows recycle of the donor wafer, but typically requires heating the implanted and bonded pair to temperatures approaching 500° C.
The use of high resistivity semiconductor-on-insulator (e.g., silicon-on-insulator) wafers for RF related devices such as antennae switches offers benefits over traditional substrates in terms of cost and integration. To reduce parasitic power loss and minimize harmonic distortion inherent when using conductive substrates for high frequency applications it is necessary, but not sufficient, to use substrate wafers with a high resistivity. Accordingly, the resistivity of the handle wafer for an RF device is at least 50 Ohm-cm, and more commonly greater than about 500 Ohm-cm. A very high resistivity semiconductor substrate, such as a silicon wafer, is prone to formation of high conductivity charge inversion or accumulation layers at the BOX/handle interface which reduce the effective resistivity of the substrate and give rise to parasitic power losses and device nonlinearity when the devices are operated at RF frequencies. See FIG. 1, which depicts a high resistivity silicon-on-insulator structure 1 comprising a P-type handle substrate 2, a buried oxide layer 4 having positive charges 6, and a silicon device layer 8. An N-type inversion layer 10 forms at the interface of the buried oxide layer 4 having positive charge 6 and the P-type handle substrate 2. These inversion/accumulation layers 10 can be due to BOX fixed charge, oxide trapped charge, interface trapped charge, and even DC bias applied to the devices themselves.
Methods have been developed to trap the charge in any induced inversion or accumulation layers so that the high resistivity of the substrate is maintained even in the very near surface region. It is known that charge trapping layers (CTL) between the high resistivity handle substrates and the buried oxide (BOX) may improve the performance of RF devices fabricated using SOI wafers. A number of methods have been suggested to form these high interface trap layers. For example, one of the method of creating a semiconductor-on-insulator (e.g., a silicon-on-insulator, or SOI) with a CTL for RF device applications is based on depositing an undoped polysilicon film on a silicon substrate having high resistivity and then forming a stack of oxide and top silicon layer on it. A polycrystalline silicon layer acts as a high defectivity layer between the silicon substrate and the buried oxide layer. See FIG. 2, which depicts a silicon-on-insulator structure 20 comprising high resistivity substrate 22, a buried oxide layer 24, and a silicon device layer 26. A trap rich layer 28, for example, a polycrystalline silicon film, for use as a charge trapping layer between a high resistivity substrate 22 and the buried oxide layer 24 in the silicon-on-insulator structure 20. An alternative method is the implantation of heavy ions to create a near surface damage layer. Devices, such as radiofrequency devices, are built in the top silicon layer 26.
It has been shown in academic studies that the polysilicon layer in between of the oxide and substrate improves the device isolation, decreases transmission line losses, and reduces harmonic distortions. See, for example: H. S. Gamble, et al. “Low-loss CPW lines on surface stabilized high resistivity silicon,” Microwave Guided Wave Leu., 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet and J.-P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf, pp. 46-47, 2004; D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer, B. Aspar, C. Laghaé and J.-P. Raskin, “Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate,” IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C. Kerr et al. “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”, Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008. In practice, the effectiveness of a polycrystalline silicon layer as a charge trapping layer may not be sufficient to meet the performance targets for advanced SOI RF devices. In some cases, the CTL may degrade device characteristics.